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[AK4682]
AK4682
Multi-channel CODEC with 2Vrms Stereo Selector
GENERAL DESCRIPTION The AK4682 is a single chip CODEC that includes two channels of ADC and four channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. The AK4682 integrates stereo selector supporting 2Vrms I/O. The AK4682 has a dynamic range of 96dB for ADC, 102dB for DAC and is well suited for digital TV and home theater system. FEATURES ADC/DAC part Asynchronous ADC/DAC Operation 8:1 Stereo Selector for ADC Input 8:3 Stereo Selector with 2Vrms Output Buffer 2-channel 24bit ADC - 64x Oversampling - Sampling Rate up to 48kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 88dB - Dynamic Range, S/N: 96dB - Digital HPF for Offset Cancellation - Channel Independent Digital Volume (+24/-103dB, 0.5dB/step) - Soft Mute 4-channel 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - S/(N+D): 86dB - Dynamic Range, S/N: 102dB - Channel Independent Digital Volume (+12/-115dB, 0.5dB/step) - Soft Mute - De-emphasis Filter - Output Mode: Stereo, Mono, Reverse, Mute High Jitter Tolerance TTL Level Digital I/F External Master Clock Input: 256fs, 384fs, 512fs 768fs (fs=32kHz 48kHz) 128fs, 192fs, 256fs 384fs (fs=64kHz 96kHz) 128fs, 192fs (fs=120kHz ~ 192kHz) 2 Audio Serial I/F (PORTA, PORTB) - Master/Slave mode (for PORTB) - I/F format 2 PORTA: Left(24 bit)/Right(20/24 bit) justified, I S, TDM 2 PORTB: Left justified, I S I2C Bus P I/F for mode setting Operating Voltage: - Digital I/O: 2.7V 5.25V, - Analog: 4.75V ~ 5.25V and 8.5V ~ 12.6V Package: 48pin LQFP (0.5mm pitch)
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[AK4682]
LIN1 LIN2 LIN3 LIN4 LIN5 LIN6
2Vrms PORTB MCLKB BICKB LRCKB SDTOB MSB
2ch ADC RIN1 RIN2 RIN3 RIN4 RIN5 RIN6
HPF, Serial DVOL I/F
2Vrms
LOUT1
ROUT1 PORTA L1 R1 LOUT2 MCLKA BICKA LRCKA SDTIA1 SDTIA2
2ch DAC
DVOL Stereo Serial Matrix I/F
L2 2ch R2 ROUT2 DAC DVOL Stereo Matrix
Control LOUT3 I/F
SDA SCL
ROUT3
AK4682 Block Diagram
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[AK4682]
Ordering Guide
AK4682EQ AKD4682 -20 +85C Evaluation Board 48pin LQFP (0.5mm pitch)
Pin Layout
VCOM36 VCOM3 ROUT3 25 24 23 22 AVDD1 AVDD2 26 AVSS1 AVSS2 27 RIN2 RIN1 LIN2 LIN1
NC
30
36
35
34
33
32
31
29
LIN3 RIN3 NC LIN4 RIN4 NC LIN5 RIN5 NC LIN6 RIN6 DVDD1
37 38 39 40 41 42 43 44 45 46 47 48 10 2 3 12 5 11 1 4 6 7 8 9 Top View
28
LOUT3 PVSS PVDD ROUT2 LOUT2 MSB ROUT1 LOUT1 DVSS2 DVDD2 SCL SDA
AK4682EQ
21 20 19 18 17 16 15 14 13
DVSS1
SDTIA1
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SDTIA2
BICKB
LRCKA
BICKA
MCLKA
LRCKB
MCLKB
SDTOB
TVDD
PDN
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[AK4682]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name DVSS1 MCLKB TVDD LRCKB BICKB SDTOB PDN LRCKA BICKA MCLKA SDTIA1 SDTIA2 SDA SCL DVDD2 DVSS2 LOUT1 ROUT1 MSB LOUT2 ROUT2 PVDD PVSS LOUT3 ROUT3 AVDD2 AVSS2 VCOM36 VCOM3 AVSS1 AVDD1 LIN1 RIN1 NC LIN2 RIN2 LIN3 RIN3 NC LIN4 RIN4 NC I/O I I/O I/O O I I I I I I I/O I O O I O O O O I I I I I I I I Function ADC Digital Ground Pin, 0V ADC Master Clock Input Pin Output Buffer Power Supply Pin, 2.7V5.25V Channel Clock B Pin Audio Serial Data Clock B Pin Audio Serial Data Output B Pin Power-Down Mode & Reset Pin When "L", the AK4682 is powered-down, all registers are reset. And then all digital output pins go "L". The AK4682 must be reset once upon power-up. Input Channel Clock A Pin Audio Serial Data Clock A Pin DAC Master Clock Input Pin Audio Serial Data Input A1 Pin Audio Serial Data Input A2 Pin Control Data Pin Control Data Clock Pin DAC Digital Power Supply Pin, 4.75V5.25V DAC Digital Ground Pin, 0V Lch Analog Output Pin1 Rch Analog Output Pin1 PORTB Master Mode Select Pin. "L"(connected to the ground): Master/Slave mode. ORed with MSB bit. "H"(connected to DVDD2) : Master mode. Lch Analog Output Pin2 Rch Analog Output Pin2 Output Buffer Power Supply Pin, 8.5V ~ 12.6V. Output Buffer Ground Pin, 0V. Lch Analog Output Pin 3 Rch Analog Output Pin 3 DAC Analog Power Supply Pin, 4.75V5.25V DAC Analog Ground Pin, 0V Common Voltage Output Pin for Output Buffer. AVDD2 x 0.734(typ). 10F capacitor should be connected to AVSS2 externally. DAC/ADC Common Voltage Output Pin. AVDD2 x 0.6(typ). 10F capacitor should be connected to AVSS2 externally. ADC Analog Ground Pin, 0V ADC Analog Power Supply Pin, 4.75V5.25V Lch Input 1 Pin Rch Input 1 Pin No Connection. No internal bonding. This pin should be connected to the ground. Lch Input 2 Pin Rch Input 2 Pin Lch Input 3 Pin Rch Input 3 Pin No Connection. No internal bonding. This pin should be connected to the ground. Lch Input 4 Pin Rch Input 4 Pin No Connection. No internal bonding. This pin should be connected to the ground.
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[AK4682]
PIN/FUNCTION (continued)
Function Lch Input 5 Pin Rch Input 5 Pin No Connection. 45 NC No internal bonding. This pin should be connected to the ground. 46 LIN6 I Lch Input 6 Pin 47 RIN6 I Rch Input 6 Pin 48 DVDD1 ADC Digital Power Supply Pin, 4.75V5.25V Note: All digital input pins must not be left floating. Note: Analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3, LIN4, RIN4, LIN5, RIN5, LIN6, RIN6 pin) must use the AC-coupling capacitor for signal input. Note: Analog output pins (LOUT1, ROUT1, LOUT2, ROUT2, LOUT3, ROUT3 pins) must use the AC-coupling capacitor for signal output. No. 43 44 Pin Name LIN5 RIN5 I/O I I
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Pin Name LOUT1-3, ROUT1-3, LIN1-6, RIN1-6 SDTOB, LRCKB(Master), BICKB(Master) MCLKA, LRCKA, BICKA, SDTIA1-2, MCLKB, LRCKB(Slave), BICKB(Slave), MSB SDA, SCL Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be pulled-up to DVDD2.
Digital
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[AK4682]
ABSOLUTE MAXIMUM RATINGS (AVSS1, AVSS2, DVSS1, DVSS2, PVSS=0V; Note: 1) Parameter Symbol min max Power Supply TVDD -0.3 6.0 DVDD1 -0.3 6.0 DVDD2 -0.3 6.0 AVDD1 -0.3 6.0 AVDD2 -0.3 6.0 PVDD -0.3 14.0 Input Current (any pins except for supplies) IIN 10 Digital Input Voltage 1 VIND1 -0.3 DVDD1+0.3 (MCLKB pin) Digital Input Voltage 2 VIND2 -0.3 DVDD2+0.3 (PDN, LRCKA, BICKA, MCLKA, SDTIA1-2, SDA, SCL, MSB pins) Digital Input Voltage 3 VIND3 -0.3 TVDD+0.3 (LRCKB, BICKB pins) Analog Input Voltage 1 VINA1 -0.3 PVDD+0.3 (LIN1-6, RIN1-6 pins) Ambient Operating Temperature Ta -20 85 Storage Temperature Tstg -65 150 Note: 1. AVSS1, DVSS1, AVSS2, DVSS2 and PVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Units V V V V V V mA V V
V V C C
RECOMMENDED OPERATING CONDITIONS (AVSS1, AVSS2, DVSS1, DVSS2, PVSS=0V; Note: 1) Parameter Symbol min typ Power Supply (Note: 2) TVDD 2.7 3.3 DVDD1 4.75 5.0 DVDD2 4.75 5.0 AVDD1 4.75 5.0 AVDD2 4.75 5.0 PVDD 8.5 9.0 Note: 2. The AVDD1, AVDD2, DVDD1 and DVDD2 must be the same voltage. The TVDD must not exceed any of AVDD1, AVDD2, DVDD1 and DVDD2 voltage.
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
max 5.25 5.25 5.25 5.25 5.25 12.6
Units V V V V V V
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[AK4682]
ANALOG CHARACTERISTICS (Ta=25C; TVDD = 3.3V; DVDD1, DVDD2, AVDD1, AVDD2= 5.0V; PVDD = 9V; AVSS1, AVSS2, DVSS1, DVSS2, PVSS = 0V; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency = 20Hz 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified) Parameter min typ max Units Analog Input to Analog Output Characteristics (LIN1-6, RIN1-6 pin to LOUT1-3, ROUT1-3 pin) S/(N+D) Input=2Vrms 92 dB S/N Input=0ff, A-weighted 96 dB Input Impedance 40 k Maximum Input Voltage (Note: 4) 2 Vrms Gain 0 dB Analog Input (LIN1-6, RIN1-6 pin) to ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-1dBFS) fs=48kHz 80 88 dB DR (-60dBFS) fs=48kHz, A-weighted 88 96 dB S/N (input off) fs=48kHz, A-weighted 88 96 dB Interchannel Isolation (Note: 3) 90 100 dB Interchannel Gain Mismatch 0.2 0.6 dB Gain Drift 50 ppm/C Input Voltage AIN= 2.2 x AVDD1/5 2 2.2 2.4 Vrms Power Supply Rejection (Note: 5) 60 dB DAC to Analog Output (LOUT1-3, ROUT1-3 pin) Characteristics Resolution 24 Bits S/(N+D) (0dBFS) fs=48kHz 76 86 dB fs=96kHz 84 dB fs=192kHz 84 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 96 dB fs=96kHz, A-weighted 102 dB fs=192kHz 96 dB fs=192kHz, A-weighted 102 dB S/N ("0" data) fs=48kHz, A-weighted 94 102 dB fs=96kHz 96 dB fs=96kHz, A-weighted 102 dB fs=192kHz 96 dB fs=192kHz, A-weighted 102 dB Interchannel Isolation 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 50 ppm/C Output Voltage AOUT= 2 x AVDD2/5 1.85 2 2.15 Vrms Load Resistance (AC Load) 5 k Load Capacitance 30 pF Power Supply Rejection (Note: 5) 50 dB Note: 3. This value is the interchannel isolation between all the channels of the LIN1-6 and RIN1-6. Note: 4. Maximum input level that satisfy S/(N+D)>80dB. Note: 5. PSR is applied to AVDD1, AVDD2, DVDD1, DVDD2 and PVDD with 1kHz, 50mVpp.
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[AK4682]
Power Supplies Parameter Power Supply Current Normal Operation (PDN pin = "H") TVDD DVDD1+AVDD1 DVDD2+AVDD2 PVDD Power-Down Mode (PDN pin = "L"; Note: 6) TVDD DVDD1+AVDD1 DVDD2+AVDD2 PVDD
min
typ
max
Units
1 37 33 15 10 10 10 10
3 55 50 25 100 100 100 100
mA mA mA mA A A A A
Note: 6. All digital inputs including clock pins (MCLKA, MCLKB, BICKA, BICKB, LRCKA, LRCKB and SDTIA1-0) are held at DVDD1, DVDD2, DVSS1 or DVSS2.
FILTER CHARACTERISTICS (Ta=-20C ~+85C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.5 ~ 12.6V; fs=48kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note: 7) PB 0 18.9 kHz 0.1dB 20.0 kHz -0.2dB 23.0 kHz -3.0dB Stopband SB 28.0 kHz Passband Ripple PR dB 0.04 Stopband Attenuation SA 68 dB Group Delay (Note: 8) GD 16 1/fs Group Delay Distortion 0 s GD ADC Digital Filter (HPF): Frequency Response (Note: 7) -3dB FR 1.0 Hz -0.1dB 6.5 Hz DAC Digital Filter: Passband (Note: 7) -0.1dB PB 0 21.8 kHz -6.0dB 24.0 kHz Stopband SB 26.2 kHz Passband Ripple PR dB 0.02 Stopband Attenuation SA 54 dB Group Delay (Note: 8) GD 20 1/fs DAC Digital Filter + Analog Filter: FR dB Frequency Response: 0 20.0kHz 0.2 FR dB 40.0kHz (Note: 9) 0.3 FR dB 80.0kHz (Note: 9) 1.0
Note: 7. The passband and stopband frequencies scale with fs. For example, 21.8kHz at -0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz. Note: 8. The calculating delay time occurred at digital filtering. This time is from setting the input of analog s signal to setting the 24bit data of both channels to the output register of PORTB. For DAC, this time is from setting the 20/24bit data of both channels on input register of PORTA to the output of analog signal. Note: 9. 40.0kHz@fs=96kHz, 80.0kHz@fs=192kHz.
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[AK4682]
DC CHARACTERISTICS (Ta=-20C ~+85C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.512.6V) Parameter Symbol min typ max Units High-Level Input Voltage VIH 2.2 V Low-Level Input Voltage VIL 0.8 V High-Level Output Voltage ( Iout=-400A) VOH TVDD-0.4 V Low-Level Output Voltage VOL 0.4 V (Iout= -400A(except SDA pin), 3mA(SDA pin)) Iin Input Leakage Current 10 A SWITCHING CHARACTERISTICS (Ta=-20C ~+85C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.512.6V; CL= 20pF (except for SDA pin), Cb=400pF(SDA pin)) Parameter Symbol min typ max Units Master Clock Timing Frequency fECLK 8.192 36.864 MHz Duty dECLK 40 50 60 % Master Clock (Note: 10) 256fsn, 128fsd: fCLK 8.192 12.288 MHz Pulse Width Low tCLKL 27 ns Pulse Width High tCLKH 27 ns 384fsn, 192fsd: fCLK 12.288 18.432 MHz Pulse Width Low tCLKL 20 ns Pulse Width High tCLKH 20 ns 512fsn, 256fsd, 128fsq: fCLK 16.384 24.576 MHz Pulse Width Low tCLKL 15 ns Pulse Width High tCLKH 15 ns 768fsn, 384fsd, 192fsq: fCLK 24.576 36.864 MHz Pulse Width Low tCLKL 10 ns Pulse Width High tCLKH 10 ns LRCKA (LRCKB) Timing (Slave Mode) Normal mode Normal Speed Mode fsn 32 48 kHz Double Speed Mode fsd 64 96 kHz Quad Speed Mode fsq 120 192 kHz Duty Cycle Duty 45 55 % TDM 128 mode LRCKA frequency fs 32 96 kHz "H" time tLRH 1/128fs ns "L" time tLRL 1/128fs ns LRCKB Timing (Master Mode) Normal mode LRCKB frequency fs 32 48 kHz Duty Cycle Duty 50 % Power-down & Reset Timing PDN Pulse Width (Note: 11) tPD 150 ns PDN "" to SDTOB valid (Note: 12) tPDV 522 1/fs Note: 10 MCLKB supports only the normal mode (256fsn, 384fsn, 512fsn, 768fsn). Note: 11 The AK4682 can be reset by bringing the PDN pin = "L". Note: 12 These cycles are the number of LRCKB rising from PDN rising.
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[AK4682]
Parameter Symbol min Audio Interface Timing (Slave Mode) Normal mode(PORTA) BICKA Period tBCK 81 BICKA Pulse Width Low tBCKL 32 Pulse Width High tBCKH 32 LRCKA Edge to BICKA "" (Note: 13) tLRB 20 BICKA "" to LRCKA Edge (Note: 13) tBLR 20 SDTIA1-2 Hold Time tSDH 10 SDTIA1-2 Setup Time tSDS 10 Normal mode(PORTB) BICKB Period tBCK 324 BICKB Pulse Width Low tBCKL 128 Pulse Width High tBCKH 128 LRCKB Edge to BICKB "" (Note: 13) tLRB 80 BICKB "" to LRCKB Edge (Note: 13) tBLR 80 LRCKB to SDTOB (MSB) tLRS BICKB "" to SDTOB tBSD TDM 128 mode BICKA Period tBCK 81 BICKA Pulse Width Low tBCKL 32 Pulse Width High tBCKH 32 LRCKA Edge to BICKA "" (Note: 13) tLRB 20 BICKA "" to LRCKA Edge (Note: 13) tBLR 20 SDTIA1-2 Hold Time tSDH 10 SDTIA1-2 Setup Time tSDS 10 Audio Interface Timing (Master Mode) Normal mode BICKB Frequency fBCK BICKB Duty dBCK BICKB "" to LRCKB Edge tMBLR -40 BICKB "" to SDTO tBSD Control Interface Timing (I2C Bus): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first clock pulse) Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note: 14) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP Capacitive load on bus Cb 0 Note: 13 BICK rising edge must not occur at the same time as LRCK edge. Note: 14 Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 15 I2C is a registered trademark of Philips Semiconductors.
typ
max
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
80 80
64fs 50 40 20 400 0.3 0.3 50 400
Hz % ns ns kHz s s s s s s s s s s ns pF
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[AK4682]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fsn, 1/fsd, 1/fsq VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing (Normal mode)
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fsn, 1/fsd VIH VIL tLRH tLRL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing (TDM 128 mode) LRCK= LRCKB, LRCKA, BICK= BICKA, BICKB, SDTI= SDTIA, SDTO= SDTOB.
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[AK4682]
LRCK tBLR tLRB tLRS BICK
VIH VIL
VIH VIL tBSD
SDTO tSDS
50% TVDD
tSDH VIH VIL
SDTI
Audio Interface Timing (Normal mode)
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tBSD
SDTO tSDS
50%TVDD
tSDH VIH VIL
SDTI
Audio Interface Timing (TDM 128 mode)
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[AK4682]
LRCK
50% TVDD
tMBLR BICK 50% TVDD
tBSD 50% TVDD
SDTO
Audio Interface timing (Master Mode)
tPD VIH VIL tPDV
PDN
SDTO
50% TVDD
Power Down & Reset Timing
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
I2C Bus mode Timing
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[AK4682]
OPERATION OVERVIEW
System Clock
The AK4682 has two audio serial interface (PORTA, PORTB) can operate asynchronously. At each PORT, the external clocks, which are required to operate the AK4682, are MCLKA (MCLKB), LRCKA (LRCKB) and BICKA (BICKB). The MCLKA (MCLKB) must be synchronized with LRCKA (LRCKB) but the phase is not critical. The PORT A is the audio data interface for DAC and the PORTB is for ADC.
Master/Slave Mode
The MSB pin and MSB bit are internally ORed and select the master/slave mode of PORTB. PORTA is slave mode only. In master mode, LRCKB pin and BICKB pin are output pins. In slave mode, LRCKA (LRCKB) pin and BICKA (BICKB) pin are input (Table 1). The AK4682 is slave mode at power-down (PDN pin = "L"). To change to the master mode, set MSB pin "H" or write "1" to MSB bit. Until when setting MSB pin "H" or writing "1" to MSB bit, LRCKB and BICKB pins are input pins. Pull-up (or down) resistor with around 100kohm is required to prevent the floating of these input pins. PDN pin L MSB pin L H L L H MSB bit (default: "0") x x 0 1 x PORTB (ADC) BICKB, LRCKB Input (slave mode) Output "L"(master mode) Input (slave mode) Output (master mode) Output (master mode) PORTA (DAC) BICKA, LRCKA Input (slave mode) Input (slave mode) Input (slave mode) Input (slave mode) Input (slave mode) (x: Don't care)
H
Table 1. Master/Salve Mode
ADC Clock Control
In master mode (MSB bit = "1"), the CKSB1-0 bits select the clock frequency (Table 2). The external clock (MCLKB) must always be supplied except in the power-down mode. The ADC is in power-down mode until MCLKB is supplied. CKSB1 0 0 1 1 CKSB0 0 1 0 1 Clock Speed 256fs 384fs 512fs 768fs
(default)
Table 2. PORTB Master Clock Control (ADC Master Mode) In slave mode (MSB bit = "0". default), external clocks (MCLKB, BICKB, LRCKB) must always be present whenever the ADC is in normal operation mode (PDN pin = "H" and PWAD = "1"). The master clock (MCLKB) must be synchronized with LRCKB but the phase is not critical. If these clocks are not provided, the ADC may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC must be in the power-down mode (PDN pin = "L" or PWAD = "0") or in the reset mode (RSTN bit = "0"). After exiting reset at power-up etc., the ADC is in the power-down mode until MCLKB and LRCKB are input.
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[AK4682]
LRCKB fs 32.0kHz 44.1kHz 48.0kHz
128fs
-
192fs
-
MCLKB (MHz) 256fs 384fs
8.1920 11.2896 12.2880 12.2880 16.9344 18.4320
512fs
16.3840 22.5792 24.5760
768fs
24.5760 33.8688 36.8640
Sampling Speed Normal
Table 3. System clock example (ADC Slave Mode)
DAC Clock Control
External clocks (MCLKA, BICKA, LRCKA) must always be present whenever the DAC is in normal operation mode (PDN pin = "H" and PWDA = "1"). The master clock (MCLKA) must be synchronized with LRCKA but the phase is not critical. If these clocks are not provided, the DAC may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down mode (PDN pin = "L" or PWDA = "0") or in the reset mode (RSTN bit = "0"). After exiting reset at power-up etc., the DAC is in the power-down mode until MCLKA and LRCKA are input. There are two modes for controlling the sampling speed of DAC. One is the Manual Setting Mode (ACKS bit = "0") using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = "1"). 1. Manual Setting Mode (ACKS bit = "0") When the ACKS bit = "0", DAC is in Manual Setting Mode and the sampling speed is selected by DFS1-0 bits (Table 4). DFS1 0 0 1 1 DFS0 DAC Sampling Speed (fs) 0 Normal Speed Mode 32kHz~48kHz 1 Double Speed Mode 64kHz~96kHz 0 Quad Speed Mode 120kHz~192kHz 1 Not Available (Note: ADC is always in Normal Speed Mode)
(default)
Table 4.DAC sampling speed (ACKS bit = "0", Manual Setting Mode)
LRCKA fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920 11.2896 12.2880
MCLKA (MHz) 384fs 512fs 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760
768fs 24.5760 33.8688 36.8640
BICKA (MHz) 64fs 2.0480 2.8224 3.0720
Table 5. DAC system clock example (DAC Normal Speed Mode @Manual Setting Mode)
LRCKA fs 88.2kHz 96.0kHz
128fs 11.2896 12.2880
MCLKA (MHz) 192fs 256fs 16.9344 22.5792 18.4320 24.5760
384fs 33.8688 36.8640
BICKA (MHz) 64fs 5.6448 6.1440
Table 6. DAC system clock example(DAC Double Speed Mode @Manual Setting Mode)
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[AK4682]
LRCKA Fs 176.4kHz 192.0kHz
128fs 22.5792 24.5760
MCLKA (MHz) 192fs 256fs 33.8688 36.8640 -
384fs -
BICKA (MHz) 64fs 11.2896 12.2880
Table 7. DAC system clock example (DAC Quad Speed Mode @Manual Setting Mode) 2. Auto Setting Mode (ACKS bit = "1") When the ACKS bit = "1", DAC is in Auto Setting Mode and the sampling speed is selected automatically by the ratio MCLKA/LRCKA as shown in the Table 8. and the internal master clock is set to the appropriate frequency (Table 9). In this mode, the setting of DFS1-0 bits are ignored. MCLKA DAC Sampling Speed (fs) LRCKA 512fs, 768fs Normal Speed Mode 32kHz~48kHz 256fs, 384fs Double Speed Mode 64kHz~96kHz 128fs, 192fs Quad Speed Mode 120kHz~192kHz (Note: ADC is always in Normal Speed Mode) Table 8. DAC Sampling Speed (ACKS bit = "1", Auto Setting Mode)
LRCKA fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
192fs 33.8688 36.8640
MCLKA (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 -
512fs 16.3840 22.5792 24.5760 -
768fs 24.5760 33.8688 36.8640 -
Sampling Speed Normal Double Quad
Table 9. DAC System clock example (Auto Setting Mode)
DAC Audio Data Control
The DAC1, DAC2 bits select the output data for each DAC. DAC1 bit DAC1 Source Normal Mode TDM Mode TDMA bit = "0" TDMA bit = "1" SDTIA1 L1, R1 SDTIA2 L2, R2 Table 10. DAC1 Source Control DAC2 bit DAC2 Source Normal Mode TDMA bit = "0" SDTIA1 SDTIA2 TDM Mode TDMA bit = "1" L1, R1 L2, R2
0 1
(default)
0 1
(default)
Table 11. DAC2 Source Control
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[AK4682]
De-emphasis Filter
The AK4682 includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis filter is off in Double speed mode and Quad speed mode. Deemphasis of each DAC can be set individually by register. Mode 0 1 2 3 DEM11 (DEM21) 0 0 1 1 DEM10 (DEM20) 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz
(default)
Table 12. De-emphasis control
ADC Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and scales with sampling rate (fs).
Audio Serial Interface Format
Each PORTA/B can select independent audio interface format. The TDMA, DIFA1-0 bits control the audio format for PORTA and support normal mode and TDM128 mode. The DIFB1-0 bits control the audio format for PORTB and support only normal mode. The default is mode 2. In all modes the serial data is MSB-first, 2's complement format. The SDTOB pins are clocked out on the falling edge of BICKB pins and the SDTIA1-0 pins are latched on the rising edge of BICKA pins. 1. Setting for the PORTA 1-1. Normal mode: TDMA bit = "0" (default) The TDMA bit = "0" sets the AK4682 audio serial interface format to the normal mode. The DIFA1-0 bits select following eight serial data format (Table 13). Mode 0 1 2 3 DIFA1 bit 0 0 1 1 DIFA0 bit 0 1 0 1 LRCKA BICKA L/R I/O speed I/O 20bit, Right justified H/L I I 48fs 24bit, Right justified H/L I I 48fs 24bit, Left justified H/L I I 48fs 24bit, I2S L/H I I 48fs Table 13 Audio Interface Format (Normal mode.) SDTIA1-2
(default)
1-2. TDM 128 mode: TDMA bit = "1" The TDMA bits = "1" set the AK4682 audio serial interface format to the TDM 128 mode. The four channel serial data (SDTIA1, 2) is input to the SDTIA1 pin. The data of SDTIA2 pin is not used. The TDM 128 mode is not available in Quad Speed Mode. Mode 8 9 10 11 DIFA1 bit 0 0 1 1 DIFA0 SDTIA1-2 LRCKA BICKA bit start I/O speed I/O 0 20bit, Right justified I 128fs I 1 24bit, Right justified I 128fs I 0 24bit, Left justified I 128fs I 1 24bit, I2S I 128fs I Table 14. Audio Interface Format (TDM 128 mode.)
(default)
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[AK4682]
2. Setting for the PORTB 2-1: Normal mode: The PORTB supports only the normal mode. The DIFB1-0 bits select following eight serial data format (Table 15). Mode 0 1 2 3 4 5 6 7 8 9 10 11 MSB pin LRCKB BICKB L/R I/O speed I/O 0 0 0 0 24bit, L J H/L I I 48fs 0 0 0 1 24bit, L J H/L I I 48fs 0 0 1 0 24bit, L J H/L I I 48fs 0 0 1 1 24bit, I2S L/H I I 48fs 0 1 0 0 24bit, L J H/L O 64fs O 0 1 0 1 24bit, L J H/L O 64fs O 0 1 1 0 24bit, L J H/L O 64fs O 0 1 1 1 24bit, I2S L/H O 64fs O 1 x 0 0 24bit, L J H/L O 64fs O 1 x 0 1 24bit, L J H/L O 64fs O 1 x 1 0 24bit, L J H/L O 64fs O 1 x 1 1 24bit, I2S L/H O 64fs O Table 15. Audio Interface Format (Normal mode, x: Don't care. L J: Left justified.) MSB bit DIFB1 DIFB0 SDTOB
(default)
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[AK4682]
LRCK
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1
BICK (64fs) SDTO(o) SDTI(i)
23 22 12 11 10 19 18 0 8 7 1 0 23 22 12 11 10 19 18 0 8 7 1 0 23
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data
Rch Data
Figure 1. Mode 0, 4 Timing
LRCK
0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1
BICK (64fs) SDTO(o) SDTI(i)
23 22 16 15 14 23 22 0 8 7 1 0 23 22 16 15 14 23 22 0 8 7 1 0 23
Don't Care 23:MSB, 0:LSB
Don't Care
Lch Data
Rch Data
Figure 2. Mode 1, 5 Timing
LRCK
0 1 2 21 22 23 24 28 29 30 31 0 1 2 22 23 24 28 29 30 31 0 1
BICK (64fs) SDTO(o) SDTI(i)
23 22 23 22 2 2 1 1 0 0 23 22 2 2 1 1 0 0 23
Don't Care
23 22
Don't Care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3.Mode 2, 6 Timing
LRCK
0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1
BICK (64fs) SDTO(o) SDTI(i)
23 22 23 22 2 2 1 1 0 0 23 22 2 2 1 1 0 0
Don't Care
23 22
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3, 7 Timing
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[AK4682]
128 BIC K
LRCKA (m ode 8)
BICKA(128fs)
SDTIA1(i)
19 18
0
19 18
0
19 18
0
19 18
0
19
L1
32 B IC K
R1
32 B IC K
L2
32 B IC K
R2
32 B IC K
SDTIA2(i)
(D on't C are)
Figure 5. Mode 8 Timing
128 BIC K
LRCKA (m ode 9)
BICKA(128fs)
SDTIA1(i)
23 22
0
23 22
0
23 22
0
23 22
0
19
L1
32 B IC K
R1
32 B IC K
L2
32 B IC K
R2
32 B IC K
SDTIA2(i)
(D on't C are)
Figure 6. Mode 9 Timing
128 BIC K
LRCKA (m ode 10)
BICKA(128fs)
SDTIA1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
32 B IC K
R1
32 B IC K
L2
32 B IC K
R2
32 B IC K
SDTIA2(i)
(D on't C are)
Figure 7. Mode 10 Timing
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[AK4682]
128 BIC K
LRCKA (m ode 11)
BICKA(128fs)
SDTIA1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23
L1
32 B IC K
R1
32 B IC K
L2
32 B IC K
R2
32 B IC K
SDTIA2(i)
(D on't C are)
Figure 8. Mode 11 Timing
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[AK4682]
Digital Volume Control
The AK4682 has channel-independent digital volume control (256 levels, 0.5dB step). The IATL7-0, IATR7-0 bits set the volume level of each ADC channel (Table 16). The OAT1L7-0, OAT1R7-0, OAT2L7-0 and OAT2R7-0 bits set each DAC channel (Table 17). IATL7-0, IATR7-0 00H 01H 02H : 2FH 30H 31H FEH FFH Attenuation Level +24dB +23.5dB +22.0dB : +0.5dB 0dB -0.5dB : -103dB MUTE (-)
(default)
Table 16.ADC Digital Volume (IATT) OAT1L7-0, OAT1R7-0, OAT2L7-0, OAT2R7-0 00H 01H 02H : 17H 18H 19H FEH FFH
Attenuation Level +12dB +11.5dB +11.0dB : +0.5dB 0dB -0.5dB : -115dB MUTE (-)
(default)
Table 17.DAC Digital Volume (OATT) ATSAD (ATSDA) bits (Table 18, Table 19) control the transition time of attenuation. The transition between each attenuation level is the soft transition. Therefore, the switching noise does not occur in the transition. Mode 0 1 ATSAD 0 1 ATT speed 1061/fs 256/fs
(default)
Table 18. Transition time of attenuation (ADC) Mode 0 1 ATSDA 0 1 ATT speed 1061/fs 256/fs
(default)
Table 19. Transition time of attenuation (DAC)
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[AK4682]
The transition between set values is soft transition of 1061 levels in Mode 0. It takes 1061/fs (22ms@fs=48kHz) from 00H to FFH(MUTE) in mode 0. If PDN pin goes to "L", the IATL7-0, IATR7-0 (OAT1L7-0, OAT1R7-0, OAT2L7-0, OAT2R7-0) bits are initialized to 30H(18H). The ATTs goes to their default value when RSTN bit = "0". When RSTN bit return to "1", the ATTs fade to their current value.
Soft mute operation
The ADC and DAC have the soft mute function. The soft mute operation is performed at digital domain. When the SMAD/SMDA bits go to "1", the output signal is attenuated by - during ATT_DATAxATT transition time (Table 18, Table 19) from the current ATT level. When the SMAD/SMDA bits are returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATAxATT transition time. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMAD/SMDA bits (1) (1) (3)
ATT Level Attenuation
-
GD (2) AOUT GD
Notes: (1) ATT_DATAxATT transition time (Table 18, Table 19). For example, in Normal Speed Mode, this time is 1061/fs cycles (256/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. Figure 9. Soft Mute Function
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[AK4682]
Stereo Matrix Control
The AK4682 has independent stereo matrix control for DAC1 and DAC2. The PL23-20 and PL13-10 bits control each matrix. PL13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PL12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PL11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PL10 DAC1 Lch Output DAC1 Rch Output 0 MUTE MUTE 1 MUTE R 0 MUTE L 1 MUTE (L+R)/2 0 R MUTE 1 R R 0 R L 1 R (L+R)/2 0 L MUTE 1 L R 0 L L 1 L (L+R)/2 0 (L+R)/2 MUTE 1 (L+R)/2 R 0 (L+R)/2 L 1 (L+R)/2 (L+R)/2 Table 20. PL13-10: DAC1 Stereo Matrix Control Note MUTE
REVERSE
STEREO
(default)
MONO
PL23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
PL22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
PL21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
PL20 DAC2 Lch Output DAC2 Rch Output 0 MUTE MUTE 1 MUTE R 0 MUTE L 1 MUTE (L+R)/2 0 R MUTE 1 R R 0 R L 1 R (L+R)/2 0 L MUTE 1 L R 0 L L 1 L (L+R)/2 0 (L+R)/2 MUTE 1 (L+R)/2 R 0 (L+R)/2 L 1 (L+R)/2 (L+R)/2 Table 21. PL23-20: DAC2 Stereo Matrix Control
Note MUTE
REVERSE
STEREO
(default)
MONO
STEREO: Normal stereo output REVERSE: L/R Reverse output MONO: Monaural output MUTE: Mute operation
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[AK4682]
The stereo matrix control has the four channel independent soft transition using soft muting function.
DAC1 Lch Setting (Control Register)
L
(L+R)/2
R
L
R
R
ATT Level Attenuation
(1)
(1)
(1)
(3)
(3)
(1)
-
GD (2) DAC1 Lch OUT GD (2) GD (2)
L
(L+R)/2
L
R
Notes: (1) ATT_DATAxATT transition time (Table 18, Table 19). For example, in Normal Speed Mode, this time is 1061/fs cycles (256/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. Figure 10. Soft Mute Function for Stereo Matrix Control
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[AK4682]
Input Selector, Input Attenuator
The AK4682 includes 8:4 stereo input/output selectors. The AIN2-0, AOUT12-10, AOUT22-20, AOUT32-30 bits set each input channel (Table 22, Table 23, Table 24, Table 25). To select the DAC1 or DAC2, set PWAD bit = PWDA bit = PWANA bit = "1". AIN3 bit 0 0 0 0 0 0 0 0 1 AIN2 bit AIN1 bit AIN0 bit Input Selector 0 0 0 LIN1 / RIN1 0 0 1 LIN2 / RIN2 0 1 0 LIN3 / RIN3 0 1 1 LIN4 / RIN4 1 0 0 LIN5 / RIN5 1 0 1 LIN6 / RIN6 1 1 0 DAC1L/DAC1R 1 1 1 DAC2L/DAC2R x x x Mute Table 22. Input Selector (for ADC, x: Don't care) AOUT12 bit AOUT11 bit AOUT10 bit Input Selector 0 0 0 LIN1 / RIN1 0 0 1 LIN2 / RIN2 0 1 0 LIN3 / RIN3 0 1 1 LIN4 / RIN4 1 0 0 LIN5 / RIN5 1 0 1 LIN6 / RIN6 1 1 0 DAC1L/DAC1R 1 1 1 DAC2L/DAC2R x x x Mute Table 23. Input Selector (for L/ROUT1, x: Don't care) AOUT22 bit AOUT21 bit AOUT20 bit Input Selector 0 0 0 LIN1 / RIN1 0 0 1 LIN2 / RIN2 0 1 0 LIN3 / RIN3 0 1 1 LIN4 / RIN4 1 0 0 LIN5 / RIN5 1 0 1 LIN6 / RIN6 1 1 0 DAC1L/DAC1R 1 1 1 DAC2L/DAC2R x x x Mute Table 24. Input Selector (for L/ROUT2, x: Don't care) AOUT32 bit AOUT31 bit AOUT30 bit Input Selector 0 0 0 LIN1 / RIN1 0 0 1 LIN2 / RIN2 0 1 0 LIN3 / RIN3 0 1 1 LIN4 / RIN4 1 0 0 LIN5 / RIN5 1 0 1 LIN6 / RIN6 1 1 0 DAC1L/DAC1R 1 1 1 DAC2L/DAC2R x x x Mute Table 25. Input Selector (for L/ROUT3, x: Don't care)
(default)
AOUT13 bit 0 0 0 0 0 0 0 0 1
(default)
AOUT23 bit 0 0 0 0 0 0 0 0 1
(default)
AOUT33 bit 0 0 0 0 0 0 0 0 1
(default)
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[AK4682]
[Input selector switching sequence] The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 11). 1. Enable the soft mute before changing channel. 2. Change channel. 3. Disable the soft mute.
SMUTE (1) (2) (1)
D AT T Level A ttenuation
-
C hannel LIN 1/R IN 1 LIN 2/R IN 2
Figure 11. Input channel switching sequence example
The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +24dB. When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms because there is some DC difference between the channels.
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[AK4682]
Power ON/OFF Sequence
The each block of the AK4682 are placed in the power-down mode by bringing PDN pin "L" and both digital filters are reset at the same time. PDN pin "L" also reset the control registers to their default values. In the power-down mode, the DAC outputs go to AVDD2 voltage and SDTOB pin goes to "L". This reset must always be done after power-up. In slave mode, after exiting reset at power-up etc., the DAC (ADC) starts to operate from the rising edge of LRCKA (LRCKB) after MLCKA (MCLKB), and then the device is in the power-down mode until MCLKA (MCLKB) and LRCKA (LRCKB) are input. In slave mode, the DAC (ADC) starts to operate by the input of MLCKA (MCLKB) after exiting reset. The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTOB becomes available after 522/fs cycles of LRCKB clock. In case of the DAC, an analog initialization cycle starts after exiting the power-down mode. The analog outputs are AVDD2 voltage during the initialization. Figure 12 shows the sequences of the power-down and the power-up. The ADC and all DACs can be powered-down individually by PWAD and PWDA bits. These bits don't initialize the internal register values. When PWAD bit = "0", the SDTOB pin goes to "L". When PWDA bit = "0", the DAC outputs go to AVDD2 voltage. Since some click noise may occur, the analog output should muted externally if the click noise influences system application.
Power PDN
522/fs
(1)
ADC Internal State DAC Internal State ADC In (Analog) ADC Out (Digital) DAC In (Digital)
"0"data (4)
Init Cycle 516/fs
Normal Operation
Power-down
(2)
Normal Operation GD (3) GD Power-down
Init Cycle
(5)
"0"data
"0"data
"0"data GD
(3)
GD
DAC Out (Analog) Clock In
MCLK,LRCK,SCLK
Don't care
(6)
(6)
(6)
(7)
Don't care
External Mute
(8)
Mute ON
Mute ON
Notes: (1) The analog part of ADC is initialized after exiting the power-down state. (2) The analog part of DAC is initialized after exiting the power-down state. (3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (4) ADC output is "0" data at the power-down state. (5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. (6) Click noise occurs at the rising/falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLKA (MCLKB), BICKA (BICKB), and LRCKA (LRCKB)) are stopped, the AK4682 must be in the power-down mode. (8) Please mute the analog output externally if the click noise (6) influences system application. Figure 12. Power-down/up sequence example
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[AK4682]
Reset Function
When RSTN bit = "0", ADC and DACs are powered-down but the internal register are not initialized. The DAC outputs go to AVDD2 voltage and SDTOB pins go to "L". Because some click noise occurs, the analog output should muted externally if the click noise influences system application. The Figure 13 shows the power-up sequence.
RSTN bit
4~5/fs (8) 1~2/fs (8)
Internal RSTN bit
516/fs (1)
ADC Internal State DAC Internal State ADC In (Analog) ADC Out (Digital) DAC In (Digital)
Normal Operation
Digital Block Power-down
Init Cycle
Normal Operation
Normal Operation GD (2)
Digital Block Power-down
Normal Operation GD
(3)
"0"data
(4)
"0"data
(2)
GD GD
DAC Out (Analog) Clock In
MCLK,LRCK,SCLK
(6)
(5)
(6)
(7)
Don't care
Notes: (1) The analog part of ADC is initialized after exiting the reset state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) ADC output is "0" data at the power-down state. (4) Click noise occurs when the internal RSTN bit becomes "1". Please mute the digital output externally if the click noise influences system application. (5) When RSTN bit = "0", the analog outputs go to AVDD2 voltage. (6) Click noise occurs at 45/fs after RSTN bit becomes "0", and occurs at 12/fs after RSTN bit becomes "1". This noise is output even if "0" data is input. (7) The external clocks (MCLKA (MCLKB), BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode. When exiting the reset mode, "1" should be written to RSTN bit after the external clocks (MCLKA (MCLKB), BICKA (BICKB), LRCKA (LRCKB)) are fed. (8) There is a delay about 4~5/fs from RSTN bit "0" to the internal RSTN bit "0". Figure 13. Reset sequence example
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[AK4682]
Serial Control Interface
AK4682 supports the fast-mode I2C-bus system (max: 400kHz). 1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4682 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master device. 1-1. Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE STABLE : DATA VALID
CHANGE OF DATA ALLOWED
Figure 14. Data transfer 1-2. START and STOP condition A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 15. START and STOP conditions
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[AK4682]
1-3. ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable "L" during "H" period of this clock pulse. The AK4682 will generates an acknowledge after each byte has been received. In the read mode, the slave, the AK4682 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition.
Clock pulse for acknowledge
SCL FROM MASTER
1
8
9
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge
Figure 16. Acknowledge on the I2C-bus 1-4. FIRST BYTE The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the SDA line. The most significant five bits of the slave address are fixed as "00100". The next two bits are "10". These two bits identify the specific device on the bus. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition which the master requests. A "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed.
0
0
1
0
0
1
0
R/W
Figure 17. The First Byte
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[AK4682]
2. WRITE Operations Set R/W bit = "0" for the WRITE operation of the AK4682. After receipt of the start condition and the first byte, the AK4682 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4682. The format is MSB first, and those most significant 3-bits are "Don't care".
*
*
*
A4
A3
A2
A1
A0
(*: Don't care) Figure 18. The Second Byte After receipt of the second byte, the AK4682 generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19. Byte structure after the second byte The AK4682 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4682 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten.
S T A R T Slave Address Register Address(n) S T Data(n+x) O P P A C K A C K A C K A C K
Data(n)
Data(n+1)
SDA
S
Figure 20. WRITE Operation
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[AK4682]
3. READ Operations Set R/W bit = "1" for the READ operation of the AK4682. After transmission of a data, the master can read next address's data by generating the acknowledge instead of terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4682 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 3-1. CURRENT ADDRESS READ The AK4682 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address "n", the next CURRENT READ operation would access data from the address "n+1". After receipt of the slave address with R/W bit set to "1", the AK4682 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission
S T A R T Slave Address S Data(n+x) T O P P A C K A C K A C K A C K
Data(n)
Data(n+1)
Data(n+2)
SDA
S
Figure 21. CURRENT ADDRESS READ 3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues the start condition, slave address(R/W="0") and then the register address to read. After the register address's acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4682 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission.
S T A R T S T A R T S A C K A C K A C K A C K A C K
Slave Address
Word Address(n)
Slave Address
Data(n)
Data(n+1)
S Data(n+x) T O P P
SDA
S
Figure 22. RANDOM READ
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[AK4682]
Register Map
Addr Register Name 00H Powerdown 1 01H Powerdown 2 02H Audio Data Format 03H De-emphasis/ ATT speed 04H Clock Control 05H Stereo Matrix Control 06H Input Selector Control 1 07H Input Selector Control 2 08H ADC Lch Volume 09H ADC Rch Volume 0AH DAC1 Lch Volume 0BH DAC1 Rch Volume 0CH DAC2 Lch Volume 0DH DAC2 Rch Volume D7 0 0 0 DEM21 0 PL23 AOUT13 AOUT33 IATL7 IATR7 OAT1L7 OAT1R7 OAT2L7 OAT2R7 D6 0 0 0 DEM20 ACKS PL22 AOUT12 AOUT32 IATL6 IATR6 OAT1L6 OAT1R6 OAT2L6 OAT2R6 D5 PWANA PWDA DIFB1 DEM11 DFS1 PL21 AOUT11 AOUT31 IATL5 IATR5 OAT1L5 OAT1R5 OAT2L5 OAT2R5 D4 0 PWAD DIFB0 DEM10 DFS0 PL20 AOUT10 AOUT30 IATL4 IATR4 OAT1L4 OAT1R4 OAT2L4 OAT2R4 D3 0 0 0 DAC2 0 PL13 AIN3 AOUT23 IATL3 IATR3 OAT1L3 OAT1R3 OAT2L3 OAT2R3 D2 SMAD 0 TDMA DAC1 CKSB1 PL12 AIN2 AOUT22 IATL2 IATR2 OAT1L2 OAT1R2 OAT2L2 OAT2R2 D1 SMDA 0 DIFA1 ATSAD CKSB0 PL11 AIN1 AOUT21 IATL1 IATR1 OAT1L1 OAT1R1 OAT2L1 OAT2R1 D0 RSTN 0 DIFA0 ATSDA MSB PL10 AIN0 AOUT20 IATL0 IATR0 OAT1L0 OAT1R0 OAT2L0 OAT2R0
Note: For addresses from 0EH to 1FH, data must not be written. When PDN pin goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the internal timing is reset, but registers are not initialized to their default values. Unused bits must contain a "0" data.
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[AK4682]
Register Definitions
Addr 00H Register Name Powerdown 1 Default D7 0 0 D6 0 0 D5 PWANA 1 D4 0 0 D3 0 0 D2 SMAD 0 D1 SMDA 0 D0 RSTN 1
RSTN: Internal timing reset 0: Reset. Registers are not initialized. 1: Normal operation (default) SMDA: DAC Soft Mute Enable 0: Normal operation (default) 1: All DAC outputs soft-muted SMAD: ADC Soft Mute Enable 0: Normal operation (default) 1: ADC outputs soft-muted PWANA: Power management for 2Vrms analog I/O 0: Power OFF 1: Power ON (default)
Addr 01H
Register Name Powerdown 2 Default
D7 0 0
D6 0 0
D5 PWDA 1
D4 PWAD 1
D3 0 0
D2 0 0
D1 0 0
D0 0 0
PWAD: Power-down control of ADC 0: Power-down 1: Normal operation (default) PWDA: Full-Power-down control of DAC1-2 0: Power-down 1: Normal operation (default)
Addr 02H
Register Name Audio Data Format Default
D7 0 0
D6 0 0
D5 DIFB1 1
D4 DIFB0 1
D3 0 0
D2 TDMA 0
D1 DIFA1 1
D0 DIFA0 1
DIFA1-0, TDMA: Audio format control for PORTA Refer Table 13, Table 14. DIFB1-0: Audio format control for PORTB Refer Table 15.
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[AK4682]
Addr Register Name D7 03H De-emphasis/ ATT speed DEM21 Default 0
D6 DEM20 1
D5 DEM11 0
D4 DEM10 1
D3 DAC2 1
D2 DAC1 0
D1 D0 ATSAD ATSDA 0 0
ATSDA: DAC digital Attenuator transition time control ATSAD: ADC digital Attenuator transition time control Refer Table 18, Table 19. DAC2-1: DAC Data control Refer Table 10, Table 11
DEM11-10: DAC1 De-emphasis filter control DEM21-20: DAC2 De-emphasis filter control Refer Table 12.
Addr 04H
Register Name Clock Control Default
D7 0 0
D6 ACKS 0
D5 DFS1 0
D4 DFS0 0
D3 0 0
D2 CKSB1 0
D1 CKSB0 0
D0 MSB 0
MSB: ADC Master/Slave control Refer Table 1. CKSB1-0: ADC Clock control for Master mode. Refer Table 2. DFS1-0: DAC Sampling Speed Control These settings are ignored in Auto Setting Mode. Refer Table 4. ACKS: DAC Auto Setting Mode 0: Disable, Manual Setting Mode (default) 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the DFS1-0 bits are ignored. When this bit is "0", DFS1-0 bits set the sampling speed mode.
Addr 05H
Register Name Stereo Matrix Control Default
D7 PL23 1
D6 PL22 0
D5 PL21 0
D4 PL20 1
D3 PL13 1
D2 PL12 0
D1 PL11 0
D0 PL10 1
PL13-10: DAC1 Stereo Matrix Control. Refer Table 20. PL23-20: DAC2 Stereo Matrix Control. Refer Table 21.
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[AK4682]
Addr 06H
Register Name D7 D6 D5 D4 Input Selector Control 1 AOUT13 AOUT12 AOUT11 AOUT10 Default 0 1 1 0 AIN3-0: ADC input selector control 0000: LIN1/RIN1 (default) 0001: LIN2/RIN2 0010: LIN3/RIN3 0011: LIN4/RIN4 0100: LIN5/RIN5 0101: LIN6/RIN6 0110: DAC1L/DAC1R 0111: DAC2L/DAC2R 1xxx: Mute (x: don't care) AOUT13-10: L/ROUT1 input selector control 0000: LIN1/RIN1 0001: LIN2/RIN2 0010: LIN3/RIN3 0011: LIN4/RIN4 0100: LIN5/RIN5 0101: LIN6/RIN6 0110: DAC1L/DAC1R (default) 0111: DAC2L/DAC2R 1xxx: Mute (x: don't care)
D3 AIN3 0
D2 AIN2 0
D1 AIN1 0
D0 AIN0 0
Addr 07H
Register Name D7 D6 D5 D4 D3 D2 D1 D0 Input Selector Control 2 AOUT33 AOUT32 AOUT31 AOUT30 AOUT23 AOUT22 AOUT21 AOUT20 Default 0 0 0 0 0 1 1 1 AOUT23-20: L/ROUT2 input selector control 0000: LIN1/RIN1 0001: LIN2/RIN2 0010: LIN3/RIN3 0011: LIN4/RIN4 0100: LIN5/RIN5 0101: LIN6/RIN6 0110: DAC1L/DAC1R 0111: DAC2L/DAC2R (default) 1xxx: Mute (x: don't care) AOUT33-30: L/ROUT3 input selector control 0000: LIN1/RIN1 (default) 0001: LIN2/RIN2 0010: LIN3/RIN3 0011: LIN4/RIN4 0100: LIN5/RIN5 0101: LIN6/RIN6 0110: DAC1L/DAC1R 0111: DAC2L/DAC2R 1xxx: Mute (x: don't care)
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[AK4682]
Addr 08H 09H
Register Name ADC Lch Volume ADC Rch Volume Default
D7 IATL7 IATR7 0
D6 IATL6 IATR6 0
D5 IATL5 IATR5 1
D4 IATL4 IATR4 1
D3 IATL3 IATR3 0
D2 IATL2 IATR2 0
D1 IATL1 IATR1 0
D0 IATL0 IATR0 0
IATL7-0, IATR7-0: ADC Volume level control Refer Table 16.
Addr 0AH 0BH 0CH 0DH
Register Name DAC1 Lch Volume DAC1 Rch Volume DAC2 Lch Volume DAC2 Rch Volume Default
D7 OAT1L7 OAT1R7 OAT2L7 OAT2R7 0
D6 OAT1L6 OAT1R6 OAT2L6 OAT2R6 0
D5 OAT1L5 OAT1R5 OAT2L5 OAT2R5 0
D4 OAT1L4 OAT1R4 OAT2L4 OAT2R4 1
D3 OAT1L3 OAT1R3 OAT2L3 OAT2R3 1
D2 OAT1L2 OAT1R2 OAT2L2 OAT2R2 0
D1 OAT1L1 OAT1R1 OAT2L1 OAT2R1 0
D0 OAT1L0 OAT1R0 OAT2L0 OAT2R0 0
OAT1L7-0, OAT1R7-0, OAT2L7-0, OAT2R7-0: DAC Volume level control Refer Table 17.
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[AK4682]
SYSTEM DESIGN
Figure 23 shows the system connection diagram. The evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
3.3V to 5V Digital 5V Digital Analog in
10u + 0.1u DVDD1 48 RIN4 41 RIN6 47 LIN6 46 LIN5 43 RIN3 38 RIN5 44 LIN4 40 LIN3 37 RIN2 36 LIN2 35 NC 34 NC 45 NC 39 NC 42
1 2 + 10u
DVSS1 MCLKB TVDD LRCKB BICKB SDTOB PDN LRCKA BICKA
DSP2
0.1u
3 4 5 6 7 8
Analog in
RIN1 33 LIN1 32 AVDD1 31 AVSS1 30 VCOM3 29 VCOM36 28 AVSS2 27 AVDD2 26 0.1u ROUT3 25 ++ 10u + 0.1u 10u +
AK4682EQ
5V Analog
DSP1
9
10 MCLKA 11 SDTIA1 12 SDTIA2 ROUT1 ROUT2 DVDD2 DVSS2 LOUT1 LOUT2 PVDD PVSS MSB SDA SCL
5V Analog
13
14
15
16
17
18
19
20
21
22
23
10u
Micro Controller
+
10u
+
0.1u
0.1u
24
LOUT3
9V to 12V Analog
MUTE MUTE MUTE MUTE MUTE MUTE
Digital Ground
Analog Ground 5V Digital Analog out
Figure 23. Typical Connection Diagram (Master Mode) Notes: - DVSS1, AVSS1, DVSS2, AVSS2 and PVSS must be connected the same analog ground plane.
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[AK4682]
1. Grounding and Power Supply Decoupling
The AK4682 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, DVDD1, DVDD2, TVDD and PVDD are usually supplied from analog supply in system. If AVDD1, AVDD2, DVDD1, DVDD2 and TVDD are supplied separately, the power up sequence is not critical. AVSS1, DVSS1, AVSS2, DVSS2 and PVSS of the AK4682 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4682 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD1 sets the ADC input range, AVDD2 sets the DAC analog output range. VCOM3 and VCOM36 are signal grounds of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached between these VCOM pins and AVSS1 pin eliminates the effects of high frequency noise. No load current may be drawn from these VCOM pins. All signals, especially clocks, should be kept away from the AVDD1, AVDD2, VCOM3 and VCOM36 pins in order to avoid unwanted coupling into the AK4682.
3. Analog Inputs
The AK4682 receives the analog input through the single-ended Pre-amp using external resistors. The input range is 2.2 x AVDD1/5 Vrms (typ. fs=48kHz) at each analog input pins. Each input pins are biased internally. The ADC output data format is 2's complement. The internal digital HPF removes the DC offset. The AK4682 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4682 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered on around the AVDD2 voltage. The output signal range scales with the supply voltage and nominally 2 x AVDD2/5 Vrms at each analog output pins. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is AVDD2 voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets a few mV.
5. Attention to the PCB Wiring
Attention should be given to avoid coupling with other signals on each analog input/output pins. Unused input pins among LIN1-6 and RIN1-6 pins should be left open.
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[AK4682]
PACKAGE
48pin LQFP(Unit: mm)
9.0 0.2 7.0 36 25 24 9.0 0.2
1.70Max 0.13 0.13 1.40 0.05
37
48 1 0.22 0.08 12
13
7.0
0.145 0.05 0.5 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
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[AK4682]
MARKING
AK4682EQ XXXXXXX
1
1) 2) 3) 4) Pin #1 indication Asahi Kasei Logo Marking Code: AK4682EQ Date Code: XXXXXXX (7 digits)
REVISION HISTORY
Date (YY/MM/DD) 07/04/24 07/07/02 Revision 00 01 Reason First Edition Error Correct Page 12 Contents Audio Interface Timing (Normal and TDM128 mode) were changed.
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[AK4682]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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